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Figures

  • Figure 1-1. Example Data Structure
  • Figure 2-1. Two-Component Pointer
  • Figure 2-2. Fundamental Data Types
  • Figure 2-3. Bytes, Words, and Doublewords in Memory
  • Figure 2-4. 80386 Data Types
  • Figure 2-5. 80386 Applications Register Set
  • Figure 2-6. Use of Memory Segmentation
  • Figure 2-7. 80386 Stack
  • Figure 2-8. EFLAGS Register
  • Figure 2-9. Instruction Pointer Register
  • Figure 2-10. Effective Address Computation
  • Figure 3-1. PUSH
  • Figure 3-2. PUSHA
  • Figure 3-3. POP
  • Figure 3-4. POPA
  • Figure 3-5. Sign Extension
  • Figure 3-6. SAL and SHL
  • Figure 3-7. SHR
  • Figure 3-8. SAR
  • Figure 3-9. Using SAR to Simulate IDIV
  • Figure 3-10. Shift Left Double
  • Figure 3-11. Shift Right Double
  • Figure 3-12. ROL
  • Figure 3-13. ROR
  • Figure 3-14. RCL
  • Figure 3-15. RCR
  • Figure 3-16. Formal Definition of the ENTER Instruction
  • Figure 3-17. Variable Access in Nested Procedures
  • Figure 3-18. Stack Frame for MAIN at Level 1
  • Figure 3-19. Stack Frame for Procedure A
  • Figure 3-20. Stack Frame for Procedure B at Level 3 Called from A
  • Figure 3-21. Stack Frame for Procedure C at Level 3 Called from B
  • Figure 3-22. LAHF and SAHF
  • Figure 3-23. Flag Format for PUSHF and POPF
  • Figure 4-1. System Flags of EFLAGS Register
  • Figure 4-2. Control Registers
  • Figure 5-1. Address Translation Overview
  • Figure 5-2. Segment Translation
  • Figure 5-3. General Segment-Descriptor Format
  • Figure 5-4. Format of Not-Present Descriptor
  • Figure 5-5. Descriptor Tables
  • Figure 5-6. Format of a Selector
  • Figure 5-7. Segment Registers
  • Figure 5-8. Format of a Linear Address
  • Figure 5-9. Page Translation
  • Figure 5-10. Format of a Page Table Entry
  • Figure 5-11. Invalid Page Table Entry
  • Figure 5-12. 80306 Addressing Machanism
  • Figure 5-13. Descriptor per Page Table
  • Figure 6-1. Protection Fields of Segment Descriptors
  • Figure 6-2. Levels of Privilege
  • Figure 6-3. Privilege Check for Data Access
  • Figure 6-4. Privilege Check for Control Transfer without Gate
  • Figure 6-5. Format of 80386 Call Gate
  • Figure 6-6. Indirect Transfer via Call Gate
  • Figure 6-7. Privilege Check via Call Gate
  • Figure 6-8. Initial Stack Pointers of TSS
  • Figure 6-9. Stack Contents after an Interlevel Call
  • Figure 6-10. Protection Fields of Page Table Entries
  • Figure 7-1. 80386 32-Bit Task State Segment
  • Figure 7-2. TSS Descriptor for 32-bit TSS
  • Figure 7-3. Task Register
  • Figure 7-4. Task Gate Descriptor
  • Figure 7-5. Task Gate Indirectly Identifies Task
  • Figure 8-1. Memory-Mapped I/O
  • Figure 8-2. I/O Address Bit Map
  • Figure 9-1. IDT Register and Table
  • Figure 9-2. Pseudo-Descriptor Format for LIDT and SIDT
  • Figure 9-3. 80306 IDT Gate Descriptors
  • Figure 9-4. Interrupt Vectoring for Procedures
  • Figure 9-5. Stack Layout after Exception of Interrupt
  • Figure 9-6. Interrupt Vectoring for Tasks
  • Figure 9-7. Error Code Format
  • Figure 9-8. Page-Fault Error Code Format
  • Figure 9-9. CR2 Format
  • Figure 10-1. Contents of EDX after RESET
  • Figure 10-2. Initial Contents of CR0
  • Figure 10-3. TLB Structure
  • Figure 10-4. Test Registers
  • Figure 12-1. Debug Registers
  • Figure 14-1. Real-Address Mode Address Formation
  • Figure 15-1. V86 Mode Address Formation
  • Figure 15-2. Entering and Leaving the 8086 Program
  • Figure 16-1. Stack after Far 16-Bit and 32-Bit Calls
  • Figure 17-1. 80386 Instruction Format
  • Figure 17-2. ModR/M and SIB Byte Formats
  • Figure 17-3. Bit Offset for BIT[EAX, 21]
  • Figure 17-4. Memory Bit Indexing
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