Figure 5-2 shows in more detail how the processor converts a logical address into a linear address.
To perform this translation, the processor uses the following data structures:
- Descriptors - Descriptor tables - Selectors - Segment Registers
The segment descriptor provides the processor with the data it needs to map a logical address into a linear address. Descriptors are created by compilers, linkers, loaders, or the operating system, not by applications programmers. Figure 5-3 illustrates the two general descriptor formats. All types of segment descriptors take one of these formats. Segment-descriptor fields are:
BASE: Defines the location of the segment within the 4 gigabyte linear address space. The processor concatenates the three fragments of the base address to form a single 32-bit value.
LIMIT: Defines the size of the segment. When the processor concatenates the two parts of the limit field, a 20-bit value results. The processor interprets the limit field in one of two ways, depending on the setting of the granularity bit:
TYPE: Distinguishes between various kinds of descriptors.
DPL (Descriptor Privilege Level): Used by the protection mechanism (refer to Chapter 6).
Segment-Present bit: If this bit is zero, the descriptor is not valid for use in address transformation; the processor will signal an exception when a selector for the descriptor is loaded into a segment register. Figure 5-4 shows the format of a descriptor when the present-bit is zero. The operating system is free to use the locations marked AVAILABLE. Operating systems that implement segment-based virtual memory clear the present bit in either of these cases:
Creation and maintenance of descriptors is the responsibility of systems software, usually requiring the cooperation of compilers, program loaders or system builders, and therating system.
15 0 31 0
LOGICAL +----------------+ +-------------------------------------+
ADDRESS | SELECTOR | | OFFSET |
+---+---------+--+ +-------------------+-----------------+
+------+ ! |
| DESCRIPTOR TABLE |
| +------------+ |
| | | |
| | | |
| | | |
| | | |
| |------------| |
| | SEGMENT | BASE +---+ |
+->| DESCRIPTOR |-------------->| + |<------+
|------------| ADDRESS +-+-+
| | |
+------------+ |
!
LINEAR +------------+-----------+--------------+
ADDRESS | DIR | PAGE | OFFSET |
+------------+-----------+--------------+
DESCRIPTORS USED FOR APPLICATIONS CODE AND DATA SEGMENTS
31 23 15 7 0
+-----------------+-+-+-+-+---------+-+-----+-+-----+-+-----------------+
| | | | |A| | | | | | | |
| BASE 31..24 |G|X|O|V| LIMIT |P| DPL |1| TYPE|A| BASE 23..16 | 4
| | | | |L| 19..16 | | | | | | |
|-----------------+-+-+-+-+---------+-+-----+-+-----+-+-----------------|
| | |
| SEGMENT BASE 15..0 | SEGMENT LIMIT 15..0 | 0
| | |
+-----------------+-----------------+-----------------+-----------------+
DESCRIPTORS USED FOR SPECIAL SYSTEM SEGMENTS
31 23 15 7 0
+-----------------+-+-+-+-+---------+-+-----+-+-------+-----------------+
| | | | |A| | | | | | |
| BASE 31..24 |G|X|O|V| LIMIT |P| DPL |0| TYPE | BASE 23..16 | 4
| | | | |L| 19..16 | | | | | |
|-----------------+-+-+-+-+---------+-+-----+-+-------+-----------------|
| | |
| SEGMENT BASE 15..0 | SEGMENT LIMIT 15..0 | 0
| | |
+-----------------+-----------------+-----------------+-----------------+
A - ACCESSED
AVL - AVAILABLE FOR USE BY SYSTEMS PROGRAMMERS
DPL - DESCRIPTOR PRIVILEGE LEVEL
G - GRANULARITY
P - SEGMENT PRESENT
Segment descriptors are stored in either of two kinds of descriptor table:
- The global descriptor table (GDT) - A local descriptor table (LDT)A descriptor table is simply a memory array of 8-byte entries that contain descriptors, as Figure 5-5 shows. A descriptor table is variable in length and may contain up to 8192 (2^(13)) descriptors. The first entry of the GDT (INDEX=0) is not used by the processor, however.
The processor locates the GDT and the current LDT in memory by means of the GDTR and LDTR registers. These registers store the base addresses of the tables in the linear address space and store the segment limits. The instructions LGDT and SGDT give access to the GDTR; the instructions LLDT and SLDT give access to the LDTR.
31 23 15 7 0 +-----------------+-----------------+-+-----+-+-------+-----------------+ | | | | | | | | AVAILABLE |O| DPL |S| TYPE | AVAILABLE | 4 | | | | | | | |-----------------------------------+-+-----+-+-------+-----------------| | | | AVAILABLE | 0 | | +-----------------+-----------------+-----------------+-----------------+
GLOBAL DESCRIPTOR TABLE LOCAL DESCRIPTOR TABLE
+------+-----+-----+------+ +------+-----+-----+------+
| | | | | | | | | |
|------+-----+-----+------| |------+-----+-----+------|
| | | M | | | M
+------------+------------+ +------------+------------+
| | | |
| | | |
+------+-----+-----+------+ +------+-----+-----+------+
| | | | | | | | | |
|------+-----+-----+------| |------+-----+-----+------|
| | | N + 3 | | | N + 3
|------+-----+-----+------| |------+-----+-----+------|
| | | | | | | | | |
|------+-----+-----+------| |------+-----+-----+------|
| | | N + 2 | | | N + 2
|------+-----+-----+------| |------+-----+-----+------|
| | | | | | | | | |
|------+-----+-----+------| |------+-----+-----+------|
| | | N + 1 | | | N + 1
|------+-----+-----+------| |------+-----+-----+------|
| | | | | | | | | |
|------+-----+-----+------| |------+-----+-----+------|
| | | N | | | N
+------------+------------+ +------------+------------+
| | | |
| | | |
+------+-----+-----+------+ +------+-----+-----+------+
| | | | | | | | | |
|------+--(UNUSED)-+------| |------+-----+-----+------|
| | | | | |
+------------+------------+ +------------+------------+
^ ^
+---------------------+ | +---------------------+ |
| GDTR |--+ | LDTR |--+
+---------------------+ +---------------------+
The selector portion of a logical address identifies a descriptor by specifying a descriptor table and indexing a descriptor within that table. Selectors may be visible to applications programs as a field within a pointer variable, but the values of selectors are usually assigned (fixed up) by linkers or linking loaders. Figure 5-6 shows the format of a selector.
Index: Selects one of 8192 descriptors in a descriptor table. The processor simply multiplies this index value by 8 (the length of a descriptor), and adds the result to the base address of the descriptor table in order to access the appropriate segment descriptor in the table.
Table Indicator: Specifies to which descriptor table the selector refers. A zero indicates the GDT; a one indicates the current LDT.
Requested Privilege Level: Used by the protection mechanism. (Refer to Chapter 6.)
Because the first entry of the GDT is not used by the processor, a selector that has an index of zero and a table indicator of zero (i.e., a selector that points to the first entry of the GDT), can be used as a null selector. The processor does not cause an exception when a segment register (other than CS or SS) is loaded with a null selector. It will, however, cause an exception when the segment register is used to access memory. This feature is useful for initializing unused segment registers so as to trap accidental references.
15 4 3 0
+-------------------------+-+---+
| |T| |
| INDEX | |RPL|
| |I| |
+-------------------------+-+---+
TI - TABLE INDICATOR
RPL - REQUESTOR'S PRIVILEGE LEVEL
16-BIT VISIBLE
SELECTOR HIDDEN DESCRIPTOR
+----------------+----------------------------------------+
CS | | |
|----------------+----------------------------------------|
SS | | |
|----------------+----------------------------------------|
DS | | |
|----------------+----------------------------------------|
ES | | |
|----------------+----------------------------------------|
FS | | |
|----------------+----------------------------------------|
GS | | |
+----------------+----------------------------------------+
The 80386 stores information from descriptors in segment registers, thereby avoiding the need to consult a descriptor table every time it accesses memory.
Every segment register has a "visible" portion and an "invisible" portion, as Figure 5-7 illustrates. The visible portions of these segment address registers are manipulated by programs as if they were simply 16-bit registers. The invisible portions are manipulated by the processor.
The operations that load these registers are normal program instructions (previously described in Chapter 3). These instructions are of two classes:
Because most instructions refer to data in segments whose selectors have already been loaded into segment registers, the processor can add the segment-relative offset supplied by the instruction to the segment base address with no additional overhead.